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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. b 06/08/05 issi ? copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. is61c6416al is64c6416al is62c6416al is65c6416al features is61c6416al and is64c6416al ? high-speed access time: 12 ns, 15ns low active power: 175 mw (typical) low standby power: 1 mw (typical) cmos standby is62c6416al and is65c6416al high-speed access time: 35 ns, 45ns low active power: 50 mw (typical) low standby power: 100 w (typical) cmos standby ttl compatible interface levels single 5v 10% power supply fully static operation: no clock or refresh required available in 44-pin soj package and 44-pin tsop (type ii) commercial, industrial and automotive tempera- ture ranges available lead-free available description the issi is61c6416al, is62c6416al, is64c6416al and is65c6416al are high-speed, 1,048,576-bit static rams organized as 65,536 words by 16 bits. they are fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design tech- niques, yields access times as fast as 12 ns with low power consumption. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and reading of the memory. a data byte allows upper byte ( ub ) and lower byte ( lb ) access. the is61c6416al, is62c6416al, is64c6416al and is65c6416al are packaged in the jedec standard 44-pin 400-mil soj and 44-pin tsop (type ii). functional block diagram june 2005 a0-a15 ce oe we 64k x 16 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb 64k x 16 high-speed cmos static ram
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al pin configurations 44-pin soj pin descriptions a0-a15 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input 44-pin tsop (type ii) lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a15 a14 a13 a12 a11 ce i/o0 i/o1 i/o2 i/o3 vdd gnd i/o4 i/o5 i/o6 i/o7 we a10 a9 a8 a7 nc a0 a1 a2 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd vdd i/o11 i/o10 i/o9 i/o8 nc a3 a4 a5 a6 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a15 a14 a13 a12 a11 ce i/o0 i/o1 i/o2 i/o3 vdd gnd i/o4 i/o5 i/o6 i/o7 we a10 a9 a8 a7 nc a0 a1 a2 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd vdd i/o11 i/o10 i/o9 i/o8 nc a3 a4 a5 a6 nc
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al truth table i/o pin mode we we we we we ce ce ce ce ce oe oe oe oe oe lb lb lb lb lb ub ub ub ub ub i/o0-i/o7 i/o8-i/o15 v dd current not selected x h x x x high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc 1 , i cc 2 x l x h h high-z high-z read h l l l h d out high-z i cc 1 , i cc 2 h l l h l high-z d out hllll d out d out write l l x l h d in high-z i cc 1 , i cc 2 l l x h l high-z d in llxll d in d in absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.5 w i out dc output current (low) 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (is64c/65c6416al) range ambient temperature v dd automotive -40c to +125c 5v 10% operating range (is61c/62c6416al) range ambient temperature v dd commercial 0c to +70c 5v 10% industrial -40c to +85c 5v 10%
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 5.0v. dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v dd + 0.5 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd com. ?1 1 a ind. ?2 2 auto. ?5 5 i lo output leakage gnd v out v dd com. ?1 1 a outputs disabled ind. ?2 2 auto. ?5 5 note: 1. v il = ?3.0v for pulse width less than 10 ns.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al is61c6416al/is64c6416al power supply characteristics (1) (over operating range) -12 ns -15 ns symbol parameter test conditions min. max. min. max. unit i cc 1 v dd operating v dd = v dd max ., ce = v il com. ?40 ma supply current i out = 0 ma, f = 0 ind. ?45 auto. ?50 i cc 2 v dd dynamic operating v dd = v dd max ., ce = v il com. ?50 ma supply current i out = 0 ma, f = f max ind. ?55 auto. ?60 typ. (2) ?35 i sb 1 ttl standby current v dd = v dd max ., com. ?1 ma (ttl inputs) v in = v ih or v il ind. ?1 ce v ih , f = 0 auto. ?1 i sb 2 cmos standby v dd = v dd max ., com. ? 350 a current (cmos inputs) ce v dd ? 0.2v, ind. ? 400 v in v dd ? 0.2v, or auto. ? 450 v in 0.2v, f = 0 typ. (2) ? 200 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 5v, t a = 25% and not 100% tested. is62c6416al/is65c6416al power supply characteristics (1) (over operating range) -35 ns -45 ns symbol parameter test conditions min. max. min. max. unit i cc average operating ce = v il , com. ? 10 ma current v in = v ih or v il , ind. ? 15 i i/o = 0 ma auto. ? 20 i cc 1v dd dynamic operating v dd = max., ce = v il com. ? 35 ma supply current i out = 0 ma, f = f max ind. ? 40 v in = v ih or v il auto. ? 45 i sb 1 ttl standby current v dd = max., com. ? 1 ma (ttl inputs) v in = v ih or v il , ce v ih , ind. ? 1.5 f = 0 auto. ? 2 i sb 2 cmos standby v dd = max., com. ? 5 a current (cmos inputs) ce v dd ? 0.2v, ind. ? 10 v in v dd ? 0.2v, auto. ? 15 or v in v ss + 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al read cycle switching characteristics (1) (over operating range) -12 -15 -35 -45 symbol parameter min. max. min. max. min. max. min. max. unit t rc read cycle time 12 ? 15 ? 35 ? 45 ? ns t aa address access time ? 12 ? 15 ? 35 ? 45 ns t oha output hold time 3 ? 3 ? 3 ? 3 ? ns t ace ce access time ? 12 ? 15 ? 35 ? 45 ns t doe oe access time ? 6 ? 7 ? 10 ? 20 ns t hzoe (2) oe to high-z output 0 6 0 6 0 10 0 15 ns t lzoe (2) oe to low-z output 0 ? 0 ? 3 ? 5 ? ns t hzce (2 ce to high-z output 0 7 0 8 0 10 0 15 ns t lzce (2) ce to low-z output 2 ? 2 ? 3 ? 5 ? ns t ba lb , ub access time ? 6 ? 6 ? 35 ? 45 ns t hzb lb , ub to high-z output 0 6 0 7 0 10 0 15 ns t lzb lb , ub to low-z output 0 ? 0 ? 0 ? 0 ? ns ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference level output load see figures 1 and 2 480 ? 30 pf including jig and scope 255 ? output 5v 480 ? 5 pf including jig and scope 255 ? output 5v notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested. figure 1 figure 2 ac test loads
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al read cycle no. 2 (1,3) ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il , ub or lb = v il ) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce , ub , or lb = v il . 3. address is valid prior to or coincident with ce low transition. t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ub_cedr2.eps t hzb address oe ce lb , ub d out t hzce t ba t lzb data valid read1.eps previous data valid t aa t oha t oha t rc d out address
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al write cycle switching characteristics (1,3) (over operating range) -12 -15 -35 -45 symbol parameter min. max. min. max. min. max. min. max. unit t wc write cycle time 12 ? 15 ? 35 ? 45 ? ns t sce ce to write end 9 ? 12 ? 25 ? 35 ? ns t aw address setup time 9 ? 12 ? 25 ? 35 ? ns to write end t ha address hold from write end 0 ? 0 ? 0 ? 0 ? ns t sa address setup time 0 ? 0 ? 0 ? 0 ? ns t pwb lb , ub valid to end of write 9 ? 12 ? 25 ? 35 ? ns t pwe 1 we pulse width ( oe =high) 9 ? 12 ? 25 ? 35 ? ns t pwe 2 we pulse width ( oe =low) 9 ? 12 ? 25 ? 35 ? ns t sd data setup to write end 6 ? 9 ? 20 ? 25 ? ns t hd data hold from write end 0 ? 0 ? 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 6 ? 6 ? 20 ? 20 ns t lzwe (2) we high to low-z output 3 ? 3 ? 5 ? 5 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to t he rising or falling edge of the signal that terminates the write.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = ( ce ) [ ( lb ) = ( ub ) ] ( we ). ac waveforms write cycle no. 1 ( we we we we we controlled) (1,2) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in data in valid t lzwe t sd ub_cewr1.eps
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al write cycle no. 2 ( oe is high during write cycle) (1,2) write cycle no. 3 ( oe is low during write cycle) (1) notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe v ih . data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd ub_cewr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd ub_cewr3.eps
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al write cycle no. 4 ( ub / lb back to back write) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 ub_cewr4.eps t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al data retention switching characteristics symbol parameter test condition min. max. unit v dr v dd for data retention see data retention waveform 2.0 5.5 v i dr data retention current v dd = 2.0v, ce v dd ? 0.2v com. ? 90 a v in v dd ? 0.2v, or v in v ss + 0.2v ind. ? 100 auto. ? 125 typ. (1) 50 t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns note: 1. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested. data retention waveform ( ce ce ce ce ce controlled) vdd ce vdd - 0.2v t sdr t rdr v dr ce gnd 4.5v 2.2v data retention mode
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al ordering information: is64c6416al automotive range: ?40c to +125c speed (ns) order part no. package 15 is64c6416al-15ka3 400-mil plastic soj is64c6416al-15ta3 44-pin tsop-ii is64c6416al-15tla3 44-pin tsop-ii, lead-free ordering information: is61c6416al commercial range: 0c to +70c speed (ns) order part no. package 12 is61c6416al-12k 400-mil plastic soj is61c6416al-12t 44-pin tsop-ii industrial range: ?40c to +85c speed (ns) order part no. package 12 is61c6416al-12ki 400-mil plastic soj is61c6416al-12kli 400-mil plastic soj, lead-free is61c6416al-12ti 44-pin tsop-ii is61c6416al-12tli 44-pin tsop-ii, lead-free
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/08/05 issi ? is61c6416al is64c6416al is62c6416al is65c6416al ordering information: is62c6416al commercial range: 0c to +70c speed (ns) order part no. package 35 is62c6416al-35k 400-mil plastic soj 35 is62c6416al-35t 44-pin tsop-ii industrial range: ?40c to +85c speed (ns) order part no. package 35 is62c6416al-35ki 400-mil plastic soj 35 is62c6416al-35ti 44-pin tsop-ii ordering information: is65c6416al automotive range: -40c to +125c speed (ns) order part no. package 45 is65c6416al-45ka3 400-mil plastic soj 45 is65c6416al-45ta3 44-pin tsop-ii
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 10/29/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 400-mil plastic soj package code: k notes: 1. controlling dimension: millimeters. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. reference document: jedec ms-027. seating plane 1 n e1 d e2 e b e a1 a c a2 b n/2+1 n/2 millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max no. leads (n) 28 32 36 a 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 a1 0.64 ? 0.025 ? 0.64 ? 0.025 ? 0.64 ? 0.025 ? a2 2.08 ? 0.082 ? 2.08 ? 0.082 ? 2.08 ? 0.082 ? b 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 c 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 d 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930 e 11.05 11.30 0.435 0.445 1 1.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 e1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e2 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc e 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc
packaging information issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 10/29/03 millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max no. leads (n) 40 42 44 a 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 a1 0.64 ? 0.025 ? 0.64 ? 0.025 ? 0.64 ? 0.025 ? a2 2.08 ? 0.082 ? 2.08 ? 0.082 ? 2.08 ? 0.082 ? b 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 c 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 d 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130 e 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 e1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e2 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc 9.40 bsc 0.370 bsc e 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc 1.27 bsc 0.050 bsc
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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